(a) Fields of the Invention
The present invention relates to semiconductor memory devices with capacitor elements, such as DRAMs (Dynamic Random Access Memories), and to methods for fabricating such a device.
(b) Description of Related Art
Ferroelectric capacitors start being produced in volume as elements of planar structures having a small capacity. Recently, development has been advancing of ferroelectric capacitors having three-dimensionally stacked structures in which a ferroelectric film is formed not only over a flat portion but also over a side wall portion of an insulating film as an underlying layer. The ferroelectric capacitors with the three-dimensionally stacked structures are constructed so that a contact plug electrically connected to a semiconductor substrate is arranged immediately below a lower electrode, which reduces their cell sizes to improve their packing densities. In addition to this, formation of the ferroelectric film over a step of the insulating film as an underlying layer widens the surface area of the ferroelectric film to secure a large capacitance of the capacitor.
Ahead of the development of the ferroelectric capacitors with the three-dimensionally stacked structures mentioned above, a variety of DRAM cell structures have been proposed which have high dielectric capacitors with stacked structures employing, as capacitor insulating films, high dielectric films such as PZT (Lead Zirconate Titanate ceramics) (see, for example, Japanese Unexamined Patent Publication No. H10-242418).
Hereinafter, description with reference to the accompanying drawings will be made of a conventional semiconductor memory device with a high dielectric capacitor disclosed in, for example, Japanese Unexamined Patent Publication No. H10-242418.
First, a conventional method for fabricating a semiconductor memory device will be described with reference to the accompanying drawings.
Referring to FIG. 9A, a field oxide film 102 and a gate insulating film are formed on a substrate 101, and then a first polysilicide film is formed on the entire surface of the substrate 101. The first polysilicide film is patterned to form a word line 103. Subsequently, ion implantation using the word line 103 as a mask is performed to form a diffusion layer 104 in a surface portion of the substrate 101.
Next, a first interlayer insulating film 105 is deposited over the entire surface of the substrate 101 and the deposited film is planarized. A contact hole reaching the diffusion layer 104 is formed through the first interlayer insulating film 105, and the contact hole is filled with a polysilicon film to form a bit line contact 106. Thereafter, a second polysilicide film is deposited over the entire surface of the substrate 101, and then the second polysilicide film is patterned to form a bit line 107 and an etch stop layer 107d. 
As shown in FIG. 9B, a second interlayer insulating film 108 is deposited over the entire surface of the substrate 101 and the deposited film is planarized. Thereafter, a silicon nitride film 109 is deposited on the second interlayer insulating film 108. In an area to be formed with a storage node contact, a contact hole is formed which passes through the silicon nitride film 109, the second interlayer insulating film 108, the bit line 107, the bit line contact 106, and the first interlayer insulating film 105 to reach the diffusion layer 104. Subsequently to this, a polysilicon film is deposited over the entire surface of the substrate 101 and the deposited film is planarized to form a storage node contact 110 made by filling the contact hole with the polysilicon film.
Then, a polysilicon film and a silicon oxide film are sequentially deposited over the entire surface of the substrate 101, after which these films are patterned in cylindrical shapes to form sacrifice layers 120 and 120d, a bottom portion 111a of a storage node electrode, and a bottom portion 111ad of a dummy electrode.
As shown in FIG. 9C, a polysilicon film is conformally deposited over the entire surface of the substrate 101, and then the deposited film is anisotropically etched back to form a side wall portion 111b of the storage node electrode around the sacrifice layer 120 and a side wall portion 111bd of the dummy electrode around the sacrifice layer 120d. In the manner described above, the storage node electrode bottom and side-wall portions 111a and 111b constitute the storage node electrode 111, and the dummy electrode bottom and side-wall portions 111ad and 111bd constitute the dummy electrode 111d. 
As shown in FIG. 10A, the sacrifice layers 120 and 120d are removed, and the remaining storage node electrode 111 and dummy electrode 111d are conformally coated sequentially with a capacitor insulating film 112 and a polysilicon film serving as a plate electrode 113. Then, the polysilicon film, the capacitor insulating film 112, and the silicon nitride film 109 are patterned to form a capacitor 114 and a dummy pattern 114d. 
As shown in FIG. 10B, a third interlayer insulating film 115 is deposited over the entire surface of the substrate 101 and the deposited film is planarized. Then, a photoresist pattern 121 with openings 121a to 121c is formed. As shown in FIG. 10C, dry etching using the photoresist pattern 121 as a mask is performed to form a contact hole 122a for the plate electrode in the second and third interlayer insulating films 108 and 115, and a contact hole 122b reaching the impurity diffusion layer 104 and a contact hole 122c reaching the word line 103 in the first to third interlayer insulating films 105, 108, and 115. Thereafter, as shown in FIG. 11, an upper-layer interconnect 116, a plate connection electrode 117, a diffusion-layer connection electrode 118, and a word-line connection electrode 119 are formed in the respective contact holes 122a to 122c. 
The conventional semiconductor memory device fabricated through the above process steps is constructed as shown in FIG. 11. To be more specific, over the substrate 101, the word line 104, the bit line 107, the capacitor 114, and the upper-layer interconnect 116 are vertically stacked from bottom to top with the first to third interlayer insulating films 105, 108, and 115 interposed between the respective components, and the diffusion-layer connection electrode 118 and the word-line connection electrode 119 extend in vertical alignment with each other with the first to third interlayer insulating films 105, 108, and 115 interposed therebetween. Note that since the bit line 107 and the capacitor 114 are typically arranged at three-dimensionally displaced positions from each other, the bit line 107 and the capacitor 114, both of which also include associated contact portions with the substrate 101, do not exist in the same cross section in the actual device. However, for convenience in description, they are shown in the same cross section in FIG. 11.